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Recent content by yuanqi

  1. Y

    synthesize error: Slice out of range

    Thanks for your quick reply. To test the possibility of shifted window structure, I write a very simple code as: and it is synthesis-able. The only difference I can tell is I use 0 instead of temp3'LOW. But the range of temp3 is [7 downto 0]. Quite confused right now! Anyway, your approach...
  2. Y

    synthesize error: Slice out of range

    Hi guy, I met an error when I do the synthesis. Here is the code: temp2:=temp3(temp3'LOW+to_integer(Shift)+3 DOWNTO temp3'LOW+to_integer(Shift)); temp3 is 8-bits wide, and temp2 4-bits wide. I want temp2 to be a window of temp3, and the signal Shift control the position of that window. shift...
  3. Y

    about power-up initialization

    Hi guys, I'm thinking about the necessity of power-up initialization. If I will definitely read the data from register after writing something into it, may I just leave it uninitialized? In other words, I use the register like RAM, we won't initialize the RAM, are we? Thanks a lot.
  4. Y

    Synopsys to cadence importing netlist..........

    The synthesized netlist is verilog code as well, which should be simulated by all the simulation tools including modelsim, cadence etc.
  5. Y

    Databus in multiprocess Soc: tristate or MUX?

    Thanks for your quick reply. Does it mean if I want to make the description consistent with real circuits, it would be better to use MUX? And if the tristate is available in the process, I can use only one global databus for the whole PEs?
  6. Y

    Databus in multiprocess Soc: tristate or MUX?

    Hi guys, From several materials I saw that it's not allowed to use tristate in lower level design. So if I have lots of PEs, say 64, whose databus is 32-bit wide. Then the input of a huge MUX will be at the order of 2K bits. I'm afraid it will cause some problems in routing&mapping. How should I...
  7. Y

    IO pads insertion UMC 90 nm in Cadence tools

    It seems synopsys does have the commands to add pads, so it would be better to use that?
  8. Y

    help--red rhombus in Encounter?

    sorry for the further disturbance, could you explain more about the "placement blockage"? Because the routing is after placing cells, do I need to come back to the previous step?
  9. Y

    help--red rhombus in Encounter?

    Thanks man!
  10. Y

    help--red rhombus in Encounter?

    Thanks a lot for your reply! But what can I do with that? And why there is no problem when I ignore this information and continue to do the final routing and geometry check?
  11. Y

    IO pads insertion UMC 90 nm in Cadence tools

    Hi dkg.sonu, did you add the pad in your netlist manually, or there is some commands to do that? Thanks
  12. Y

    help--red rhombus in Encounter?

    Hello everyone, I'm using Encounter to implement my circuit. But I met some notices like red rhombus without warnings. Could anyone tell me what does it mean please? Thanks very much! What's more, this kind of white squire is baffling as well. Any help please!
  13. Y

    The change of instance name through synthesis!

    Thanks a lot! It looks promising!
  14. Y

    The change of instance name through synthesis!

    Hello everyone, I used the GENERATE statement to instantiate multiple entities in my top level design. After synthesis, the name of every instantiation is added by a backslash at the beginning, shown in the figure. The consequence is that the the names in netlist file are not consistent with...
  15. Y

    SDF file cannot find the lower level instance!

    YES! You are right, the RTL complier has added a backslash at the beginning of some instances. I think it's due to incompatibility between the synthesizer and VHDL code, I think I could avoid it by writing Verilog. Thanks a lot
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