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Recent content by ys82

  1. ys82

    bluetooth sync word calculate in access code

    i meet a issue of bluetooth sync word calculate, can anybody help me ? thank you very much !! the bloouth spec about sync word calculate as bellow: 1. Generate information sequence; 2. XOR this with the “information covering” part of the PN overlay sequence; 3. Generate the codeword; 4. XOR...
  2. ys82

    can anybody provide the datasheet or material of CIU96

    I need some the datasheet of CIU96, also some material of CIU96, many thanks
  3. ys82

    can anybody give me some description of the following IO

    thanks ! so can I think these three(DUP/CUP/BOAC) have the same meaning， they are referring to active layout structures under the bonding pad ？ What are the advantages of putting active layout structures under the bonding pad ?
  4. ys82

    can anybody give me some description of the following IO

    circuit under pad cup io Can anybody give me some introduce of the following IO type and the difference between these IO type: 1.DUP （device under pad） 2.CUP (circuit under pad) 3.BOAC (Bonding On Active Circuit) is there any document to introduce these IO type. many thanks !
  5. ys82

    whether to Integrate IP into chip would save power ?

    I want to kown whether integrate off-chip memory and other peripherals into chip would save power ? If yes, why do this can save power ?
  6. ys82

    Timing optimization of scan paths

    you can set some input/output delay on scan_in/scan_out. I think the ATE tester can give the reference value
  7. ys82

    about the 8x8 macro block for JPEG

    jpeg macro block I want to design a asic block for JPEG encoder, But I'm confused with the scan of JPEG standard: "input block by block from left to right, and block-row by block-row from top to bottom". But images are usually captured a line at a time, the cmos sensor output pixel data line...
  8. ys82

    PIPELINED JPEG encoder in VERILOG (Source Code)

    encoder in verilog thanks ,, is there any document ?
  9. ys82

    jpeg & mjpeg encoder using verilog need suggestions

    jpeg & mjpeg encoder Does anybody used the IP "video_compression_systems" from opencore, （designed by “Richard Herveille”）， I want design a jpeg&mjpeg encoder using verilog, so can anybody give me some suggestions about how to implement the encoder ? many thanks
  10. ys82

    Discrete cosine transform .. help!!

    Thanks a lot
  11. ys82

    can anybody provide the document of m-jpeg standard

    can anybody provide the document of m-jpeg standard, thanks
  12. ys82

    power ring width of memory

    memory compiler can generate the spec of memory, there is a table for some parameter(include peak current). Is there a effective way to generate memory with appropriate power-ring at the beginning of Design
  13. ys82

    power ring width of memory

    Do you mean that I need to calculate the resistance of memory's power-ring, then using following formula to see Whether the power-ring width is ok: (peak current) x (resistance of memory's power-ring) < maximum voltage drop limit But when I using memory compiler to generate memory , It give a...
  14. ys82

    power ring width of memory

    hi I would like to know how to decide the width of memory power ring when using artisan memory compiler? Thanks!
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