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young

Recent content by young

Y
How to add delay in CPLD?

it may be using sample skill
- young
- Post #3
- Mar 14, 2005
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Y
Powerpcb to Cadence conversion

cadence to pads conversion I think it is unnecessary.you can export to spectra.
- young
- Post #4
- Mar 5, 2005
- Forum: PCB Routing Schematic Layout software and Simulation programs
Y
how about simulator developed by xilinx itself?

what is your opinion?thx
- young
- Thread
- Mar 5, 2005
- Replies: 15
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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