Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by yoran

  1. Y

    [verilog] assign wire to register in loop

    Thanks for the reply. So you kind of have to create this "artificial" module to make it work? Maybe it's because generate statements only work for module instantiation?
  2. Y

    [verilog] assign wire to register in loop

    Hey, I have a question about Verilog. I have a bunch of wires h_in[0:(16*640)-1] as an input in a module. They represent 640 values of 16 bits. I want to store those into registers, so reg signed [0:16-1] h[0:639]; h[0] <= h_in[0*16:(0+1)*16-1]; h[1] <= h_in[1*16:(1+1)*16-1]; h[2] <=...
See more

Part and Inventory Search

Back
Top