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Recent content by yonehara

  1. Y

    [question] DRC fix in SOC Encounter

    neither pre nor in-place optimization.. this is the problem? What happen in in-place and pre-place optimization? I will try this way, with both optimization.
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    [question] DRC fix in SOC Encounter

    Well, LEF file is provided, you are talking about IMPORT DESIGN STAGE, right? if yes, anyway i got these DRC vios. What is the explanation about it? my design is simple, no hard macros, only the std cell block to floorplan i'm a noob (first big project) and design density is something about 75%...
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    [question] DRC fix in SOC Encounter

    Hi, i have found many DRC problems after nano route. Such as open and antenna violations. Open Violation is the most frequent and I dont know what I have to do to solve this problem!! My doubt is, from when I can extract the GDSII and further files to solve this on Virtuoso? Can i solve this on...
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    Difference between LM_LICENSE_FILE and CDS_LIC_FILE

    Hi, I have wondered what is the difference between the LM_LICENSE_FILE and CDS_LIC_FILE? What Should I do in regarding each one?
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    RTL Compiler: check_design command

    Thank you man! I really have enjoyed your help. If you need something and, of course if I would be able to help you. Dont hesitate to request. Tanks. Just for curiosity, where are you from and where you are? tanks a lot.
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    RTL Compiler: check_design command

    Thank you kbulusu. Im from Brazil and I have been coursing the IC Brazil Program phase 3. OJB (on job training) at the UFMS (Federal University of Mato Grosso do Sul) We have the license for CAdence academic. I got the explanation about clock, tanks a lot. I need to get the rtl synthesis done...
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    RTL Compiler: check_design command

    Sorry for the uncleared post, and my English. Could you report if my English texts are clearly understandable? or comprehensible? I've just tried an elaboration, generic and to mapped synthesis, then I've also extracted the netlist from rtl compiler by write_hdl command and write_sdf for the...
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    RTL Compiler: check_design command

    It does not work... :( But, now with the netlist mapped, the simulation consider the time. I have set the timescale to 1ns/1ps, the clock testbench 1000 time units and SDC clock 100. create_clock -name CLOCK -period 100.0 -waveform {50.0 100.0} [get_ports {clk}] Are there any inconsistency...
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    RTL Compiler: check_design command

    Hi kbulusu, until the elaboration, the results are the same. Then I'm going to report you the read_sdc and read_vcd command issues I've gotten. read_sdc command output: read_sdc $CONSTRAINTS_PATH/rvex.sdc Removing external delay 'create_clock_delay_domain_1_CLOCK_R_0'. Info : Removed...
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    RTL Compiler: check_design command

    I'm going to home now. When i got there, i will do this and post the results. tank you!!
  11. Y

    RTL Compiler: check_design command

    here im gonna post some lines of my script: set_attr hdl_search_path /home/felipe/Desktop/r-vex_r38_MSc/r-VEX/synthesis/rtl/ / set_attr lib_search_path $LIBRARY_PATH/ set_attr library $LIBRARY_PATH/liberty/c35_3.3V/c35_CORELIB.lib #set_attr avoid true OAI212 #set_attr...
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    RTL Compiler: check_design command

    But after synthesis, the design still has unloaded pins. I've found pin blocks floating through the whole design, some blocks are clear from these issues, but others not. The problem is after synthesize -to_map command. I have extracted out the netlist, but the design functionality has been...
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    RTL Compiler: check_design command

    So, after the elaboration on both RTL Compiler versions and same rtl. I got these issues. using 8.1: Checking the design. Check Design Report -------------------- Summary ------- Name Total -------------------------------------- Unresolved References...
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    RTL Compiler: check_design command

    Hi everybody, I'm using rtl compiler 8.1 and i've elaborated my design on it. I got some issues in the summary. May you help me telling me what is important and what I don't need to worry about? I would really appreciate any help. tks.
  15. Y

    Encounter RTL Compiler

    try this command find <lib_directory> -name "*.lbr|lib" -print You can use either .lbr or .lib files as library the RTL Compiler will accept.
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