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hello ,
can anyone please help me , that my set up time is independent of capacitive load and i am not getting any explanation for that. i extracted my h spice net list from cadence virtuoso layout editor with 45nm technology.also, my setup time is linear with data transition time up to...
hiiiiii,
i having inverter followed by transmission gate, having a linear delay between input an doutput w. r.t input transition time. can u please tell me the reason for that. also, can someone tell me the reasons why generally,delay is linear function of load and transition time
are u sure that setup time is independent of output load, can u give me good reasons for that, anything else concerning this topic is also needed,please help me .
---------- Post added at 10:29 ---------- Previous post was at 10:28 ----------
yes,it is output load but i m not using any...
my set up of D-latch is coming independent of capacitive load,is this possible?
if it is not, then can u please tell me where am i doing wrong?
i extracted my D-latch netlist from virtuoso layout editor and working on H-spice.
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