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@ TrickyDicky
Actually I'm doing formal verification for a encoding unit. This encoding unit has a 3D signal which stores the encoded data. For me, That signal is an input So I need to declare this signal inside the port as an input. Hence I created a package for this specific data type. Here is...
Hi,
I need to declare a 3D array as an input inside the entity.
I created a library like this
type my_2d_array : is array ( 0 to m ) of std_logic_vector(0 to k) ;
type my_3d_array : is array ( 0 to n ) of my_2d_array ;
I used my_3d_array as my data type and compile done perfectly. But when I...
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