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Recent content by Yoga Nanda

  1. Y

    Writing a verilog code for a crossbar switch

    module crbar(y1,y2,x1,x2,s); output y1,y2;[/CODE] input x1,x2; input s; assign y1=((~s&x1)|(s&x2)); assign y2=((~s&x2)|(s&x1)); endmodule
  2. Y

    design considerations

    what are the design considerations needed for cmos analog design ,like inverter and differential amplifier?:?:
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