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Recent content by ykishore

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    Question on ADC/Sampling and Images

    Say I have a sensor that generates a signal of freq 30Hz and now when I sample this at 100Hz, which is above the 2fa; The Nyquist criteria is satisfied. But the output of the sampler has lot of frequencies right i.e., 30Hz, 100-30=70, 100+30=130, 200-30=170, 230.... Now if I dont do any...
  2. Y

    signal loss on a perfectly matched transmission line

    If a transmission line is terminated perfectly with a load resistance equal to its characteristic impedance, does this mean only half of the input signal reaches the load? I mean like if we consider the characteristic impedance as a lumped resistance, say Z0, now the load Rs=Z0, as its perfectly...
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    Layout for ADCs (Analog 2 Digital conv)

    PCB Layout for ADCs (Analog 2 Digital conv) Hi I was looking at some material on recommendations for ADCs and came across the following: So in ADCs we always need to connect both the analog and digital power/gnd pins to low noise analog planes? Why is that?
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    Any Good reference for Board design

    Is there a good reference book/material to learn all the intricacies of PCB design and various techniques to be adopted? - - - Updated - - - Just to make it more clear, I am looking for reference on basic guidelines without going into too much of details with math on transmission lines etc
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    Why are upper Metal layers wider

    Why are upper Metal layers wider than the lower ones? Is that due to lithography reasons? Say if we layout a lower layer wider than the min required and same width as one of the upper layers, which of these offer low resistance? i.e., among a M1 of width W and M3 of same width W, which of these...
  6. Y

    Verilog error with for loop

    I am trying to synthesize the following code integer i; always @(posedge clk) begin for (i=0; i<61; i = i+1) begin if(data[i+3:i]==4'b0000) begin occurrences[i]=1'b1; end else occurrences[i]=0; end end It keeps giving me an...
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    SDC constraints for clock domain crossing

    I am doing CDC on FPGA. Even for ASIC, if we are doing CDC using STA tool, how do we do it? We should be indicating the crossing path as false path through clock grouping asynchronous option isnt it? or do we give some other constraints to indicate CDC in ASIC?
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    IP support in Xilinx Vs Altera

    Usually when comparing between Xilinx and Altera FPGAs, one of the common statements that I keep coming across is that Xilinx has more IP core support than Altera. I am just curious, if anyone knows of specific examples, as in if there are any cores in Xilinx that Altera doesn't provide or is...
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    SDC constraints for clock domain crossing

    What are the various SDC constraints that we need to take care of while doing clock domain crossing? I know one is we do clock grouping as asynchronous and set_max_delay or set_max_skew. But are there any others? Especially when we have a data bus with a valid signal crossing clocks?
  10. Y

    Return to zero circuit

    Well, let me make it clear The question is I want to design a NRZ circuit that generates the waveform shown. One way of doing it is just using delay and a high-pass latch. But I am just curious if there is any other way of doing it. Thanks
  11. Y

    Return to zero circuit

    Design a RZ (return to zero )circuit.
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    Clock divider circuit

    If I have a clock of frequency F; I need a digital circuit that can generate frequency (M*F)/N; need Not be a programmable one for eg: given a clock of freq, a circuit to generate 2/3*F freq?
  13. Y

    Digital logic design problem

    Will this design work satisfactorily? Assumptions: thold = tsetup = tclock_out = tclock_skew = 1ns. After reset A = 0, B = 1
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    significance of frequency in power supply

    So do you mean that the manufacturers make TVs in one way for India and in an other way for US?
  15. Y

    operating at insufficient power

    is the case same with equipment like washing machines? Because usually my mother scolds me if I overload our washing machine with too many clothes. Will it really get damaged?
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