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Recent content by yinhexi

  1. Y

    need your help for a low noise analog buffer

    thank you ! mtwieg, let me take a try!:-D
  2. Y

    need your help for a low noise analog buffer

    i need one low noise buffer to driver a large cap(about 30PF), the spec. of noise is <100uV,the spec. of GBW is about 40MHz, anayone would like to give me an advice？ thank you for reading this issue！
  3. Y

    need help:time variation resistor modeling with veriloga

    i want to modle a time variation resistor with noise power 4kTR,but I have no idea how to do. any one can help me? need your help
  4. Y

    is it possible to design a ex-cap-free ldo use in digital circuit?

    thank you！erikl, we do need a pin for this ldo. ---------- Post added at 02:18 ---------- Previous post was at 02:16 ---------- thank you! upvl , this structure is very interesting ，and i think it is helpful to me
  5. Y

    is it possible to design a ex-cap-free ldo use in digital circuit?

    thank u erikl！ i have read the paper you suggested to me， and am afraid that it may not be available for me. my circuit need current about 20mA ,but it have a very large and very quick peak value，so this structure is not suitable because of poor transient response. the loading current change...
  6. Y

    is it possible to design a ex-cap-free ldo use in digital circuit?

    the digital circuits' average current is about 20mA，and the peak value is aboat 200mA，my chip is now pad-number limited，so i have no pad for ex-cap， anyone who have ideas about cap-free ldo for my situation？ thank you！
  7. Y

    Strange response in a circuit - need verification

    Re: Strange resp. if you use a ideal vsource as supply, other component are useless
  8. Y

    post simulation problems with ultrasim

    design with TSMC 0.18um lib, the post netlist is not hierarchy,so i use ultrasim to tradeoff the speed and accuracy the problem is: this mos model is binning model(scalable),there are 20 sub-models in every mos type, nch.0 , nch.1 , nch.2 .... for nch (digital nchannal transistor). my usim_opt...
  9. Y

    post simulation problems with ultrasim

    design with TSMC 0.18um lib, the post netlist is not hierarchy,so i use ultrasim to tradeoff the speed and accuracy the problem is: this mos model is binning model(scalable),there are 20 sub-models in every mos type, nch.0 , nch.1 , nch.2 .... for nch (digital nchannal transistor). my usim_opt...
  10. Y

    how to simulate the noise of close loop pll with SpectreRF?

    i take the same way for vco ,but failed!!! need your help! thanks!
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