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Recent content by yilmi shin

  1. Y

    I have negative slack after CTS, what is the problem in my sdc?

    Thanks for your attention !! CTS engineer checked the reasons. this design had the feedback loops. it is not recommended. but I just implemented the design as the algorithm. CTS engineer guess ; because of the loop, u_count_x/CK has too many inverters/buffers after CTS. So, I changed the...
  2. Y

    I have negative slack after CTS, what is the problem in my sdc?

    in my sdc create_clock CLK_A create_generated_clock CLK_B -divide 1 create_generated_clock CLK_C -divide 7 in my design CLK_A - BUF -> CLK_B CLK_B feed u_count_X CLK_B feed u_ff_m CLK_C is u_ff_m/Q CLK_C feed u_carry_X u_ff_m/D is the combinational logic using u_count_x/Q u_count_x/D has...
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