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Recent content by Yikun

  1. Y

    The problem about using cadence assura tool

    There is no "/usr/cadence/IC615/share/oa/bin/linux_rhel30_gcc44x_32/opt" in my system, but there is "/usr/cadence/IC615/share/oa/bin/linux_rhel30_gcc411_32/opt", I don't know why. Before, I installed NCSU FreePDK45, maybe this prcocess I changed some setting unintended.
  2. Y

    The problem about using cadence assura tool

    When I start assura independently by using command "avv", there is error message "ERROR: oaGetLibPath cannot be executed because the /usr/cadence/IC615/share/oa/bin/linux_rhel30_gcc44x_32/opt", anyone had this problem before, please help me. Thanks very much in advance.
  3. Y

    Need help, NCSU FreePDK45, non-SKILL Pcell, not supported in Virtuoso

    The NCSU FreePDK45 is not Pcell, it's Pycell, that's why Virtuoso doesn't support, but I have already install the Pycell Studio, it's suppose to help Vitruoso to support the Pycell, but it doesn't work. I don't know what happened, or something I did wrong.
  4. Y

    Need help, NCSU FreePDK45, non-SKILL Pcell, not supported in Virtuoso

    I have installed NCSU FreePDK45 design kit for Cadence IC615 but have problem instantiating device layout with the following warning. *WARNING* (DB-220704): The Pcell super master: NCSU_TechLib_FreePDK45/nmos_vtl/layout is not a SKILL super master. The usage of non-SKILL Pcells in Virtuoso is...
  5. Y

    Some questions about Synopsys IC Compiler and Cadence Virtuoso

    Thanks very much, that's really helpful.
  6. Y

    NCSU_FreePDK45: The usage of non-SKILL Pcells in Virtuoso is not a supported feature

    I have installed NCSU FreePDK45 design kit for Cadence IC615 but have problem instantiating device layout with the following warning. *WARNING* (DB-220704): The Pcell super master: NCSU_TechLib_FreePDK45/nmos_vtl/layout is not a SKILL super master. The usage of non-SKILL Pcells in Virtuoso is...
  7. Y

    FreePDK45 P-cell problem

    I am also stuck by this problem, if you have solved it, could you tell me how to do?
  8. Y

    How to apply TSMC PDK

    Hi, everyone I am a student in college, I want to know if the TSMC supply free PDK for university, and how to apply it. Our lab has all the EDA tools, Cadence, Synopsys, but now I noticed we don't have PDK to do manual layout work. Any suggestion? Thanks very much in advance. Best
  9. Y

    I need some help on Synopsys TSV design

    I check the information from synopsys website, and it doesn't say if this TSV design need special tech lib supported or just use the normal tech lib and you need to use the tool to set contacts on different chips. I also checked TSMC website about TSV information, I still haven't figured if TSV...
  10. Y

    Some questions about Synopsys IC Compiler and Cadence Virtuoso

    I am new in the layout design, so I have some questions about the tool. What's the difference between IC Compiler and Cadence Virtuoso ? Some said ICC if for digital layout, Virtuoso is for Analogy design, that's all? The second thing, if the ICC can be used for manual design, if can, what...
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