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Recent content by yi_demon

  1. Y

    VCO Varactor Bank Control Logic Noise

    Hi all, Has anyone ever encounter the problem that huge amount of noise brought by varactor bank control logic? I tried to switch on/off the AMOS varactor bank by changing the S/D node voltage between 0 and Vdd directly. So the control logic is directly connect to varactor S/D node, not switch...
  2. Y

    IBM SOI PDK (CSOI7RF) LVS Problem

    Hello all, I'm having a problem with IBM CSOI7RF when doing LVS. IBM offers an extra node x to represent the substrate of SOI transistor and it has a internal substrate model in schematic simulation. So I just float or connect it to GND in schematic simulation. However, Assura LVS also...

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