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Recent content by YenYu

  1. Y

    FYP Project help . simple de

    for this part , i suggest u do it at ur main... ur input should be DACin,Clk,Reset ur output should be DACout from the verilog code... Also try to seperate ur main program and testbench nicely so that it wouldnt feel very messy and confusing... when i start my project that time... every pins...
  2. Y

    FYP Project help . simple de

    Oh... There's no way u can convert that Verilog to VHDL, unless u are veri strong at both language... else the onli way to convert is to buy a software which will convert the verilog to VHDL. Well, the software aint a cheap one and it is not ez to find. I suggest u get the idea of the coding...
  3. Y

    FYP Project help . simple de

    If i would to do at home, u wont be able to use it in sch. Mine is a updated version Xilinx 9.1i. I've tried b4 .... u wont be able to load it with Xilinx 8.2g. Also i dont think there is error for my project b4 i left unless some one else edited it making it not to work. If u see, in my...
  4. Y

    FYP Project help . simple de

    So which coregen u using ? i mean like DSS,multiplexer & etc? which do u use? DAC? u made a program urself(soruce code)?
  5. Y

    FYP Project help . simple de

    Prolly u used the LUT that the coreGEN haf generated.(guessing) DAC stands for Digital-Analogue Converter? Which coreGEN did u use? Wat's the purpose of it? maybe gif mi the whole story? i could help a'lil. Btw, i get a B+ onli... i guess veri few ppl or not even 1 get A unless u did go for...
  6. Y

    FYP Project help . simple de

    Yo dude... u from nyp? your project looks like my previous project... hehe.. I dont think there's a need to write the clock... u can just prolly edit from the coreGEN but from previous experience, using coreGEN isnt a good way. echo47 did also mention it before during my FYP.
  7. Y

    Help in Digital Converter with VHDL

    Does it apply to Qt2's filter also?
  8. Y

    What are the recent developments in WiMAX?

    Re: What is WiMAX Check out this lil' info. https://en.wikipedia.org/wiki/Wimax
  9. Y

    Where to start learning VHDL_AMS?

    Re: VHDL_AMS Yes.. It is possible to Simulate in ModelSim. U can get it at the Xilinx Webpage
  10. Y

    Help in Digital Converter with VHDL

    From the COREGEN setting , The Clock Freq is at 500MHz,and Sampling Freq at 250MHz. Aint it? HOw do u see? Hmm, i'm not quite sure about this.
  11. Y

    Help in Digital Converter with VHDL

    Does Fc means Frequency Cut-off?
  12. Y

    verilog code for cordic processor

    cordic implementation in verilog If u are using Xilinx, Try opening new source with IP COREGEN. There's a CORDIC which u might need it.
  13. Y

    Where to start learning HDL advanced design?

    Re: HDL advanced design If ur're using Xilinx, try using ModelSim XE for simulatio and synthesis purpose. Take a Look at this web, It could help u in ur FPGA design,synthesizer too. **broken link removed**
  14. Y

    Help in Digital Converter with VHDL

    Alrite... here's my code. I've onli include 6 files that u mentioned last time.
  15. Y

    Help in Digital Converter with VHDL

    Hmm.... Is this the one u make the COE file for mi? I'm trying on solving my Qt2, I dont know why it came out a straight line.. It's kinda confusing. I think the best way is still to solve the Qt2 b4 any proceed. What should be the cause of it?
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