Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A little help please!
Problems solved!
For some reason, I've deleted the file that defines the entity, but I forgot about it. Still, thanks for the help!
A little help please!
I don't quite understand? "Music" is just a component? Only entity can be port mapped?
I've searched another example:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX2 is
port (SEL, A, B: in STD_LOGIC;
F : out STD_LOGIC);
end;
architecture STRUCTURE of MUX2...
A little help please!
This is the section I've been having problems with:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY NoteTabs IS
PORT ( clk : IN STD_LOGIC;
ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END;
ARCHITECTURE one...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
