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Recent content by ye.hui

  1. Y

    Floating point to Fixed point conversion

    Matlab(floating) -> Matlab(fixed)-> RTL
  2. Y

    How is systemC model synthesised to the netlist?

    about systemC synthesis how do you think that systemC model is synthesised to the netlist? i mean the design is described by systemC (not RTL) , and it should be synthesised to RTL level or gate level by using some EDA tools, such as systemc compiler from synopsys.
  3. Y

    Help me with Verilog synthesis in Synplify 7.2.1

    Re: Help,about Synplify i guess the reason is the synthesis algorithm of the software if you did not change any other options and constraints. you can build a new project which is the same as the previous one, just the option "write to netlist" is defferent, and observe the results. or you can...
  4. Y

    DSP with FPGA: Verilog or VHDL ?

    maybe VHDL is better for DSP targetted to FPGA because VHDL has abundant data types to describe the algorithm.
  5. Y

    Ask about the timing in FPGA...

    you should never think about using delay circuits to implement any specified delay because the delay may be variable after each place and route. the counter is a good choice.
  6. Y

    How to start working with VirtexII pro Xilinx?

    Re: VirtexII pro Xilinx so do you use the cpu core?
  7. Y

    down-sampler & up-sampler

    sorry, it is a clerical error.
  8. Y

    down-sampler & up-sampler

    they are time invariant because if the input signal is delayed a specified time, the output signal will not be delayed the same time.
  9. Y

    What differences between direct form FIR and transpose FIR

    pipelining in dsp direct form 2 pipelining depends on the operation frequency of the FIR.i dont think you need to split the adder into two or three stages if you make a transpose filter.
  10. Y

    What to use for designing a 500 Mbps QPSK modulator

    Re: QPSK modulator you can evaluate how many MIPS the design needs to process data if you use DSP processor. i think it is not economical to implementate in DSP.
  11. Y

    How do we make consideration on the precision on filter?

    in matlab, you can use quantization functions in filter design toolbox to analyse the fixed-point filters. it is very convenient.
  12. Y

    matlab code for software radio reciever

    Re: DIGITAL RECEIVER i think you can try it in ISE. the DDC you described is not large.
  13. Y

    matlab code for software radio reciever

    Re: DIGITAL RECEIVER it depends on what the DDC is used for. for example, the DDC in WCDMA with multi-channel is larger than in many other applications.
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