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Dear Sirs:
I use PSS and PNOISE to simulate the PFD/CP combined. I set up some phase difference between reference clock and feedback clock. I suppose to see the best phase noise occurs with zero phase difference and the larger phase difference, the worse phase noise characteristic. However...
Deal All:
Does anyone have the idea of designing the deadzone of phase/frequency detector? What do ppl usually be aware of while designing the deadzone and what's the typical value of deadzone (in ps) we may have in 2 ~ 5 GHz frequency synthesizer?
Thank you!
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