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Recent content by Yathin P U

  1. Y

    Current Density for metals in 14nm

    Hi folks, I would like to know the metal densities for various metals used in 14nm process especially for metal 5 and metal 7. I do not have access to the DRM :sad: Thanks in advance!
  2. Y

    Why don't we go for fingering of the gate length of the device?

    Hi, I know we do the fingering of the width in order to reduce the output parasitic cap and share the diffusion. I would want to know why length of the device is not fingered. For an instance, if I am using 90nm pdk and one of the devices has gate length of 180nm, is it advisable to finger the...
  3. Y

    How to overcome poly density error in layout

    Hi, Please help me in solving this. How do you overcome maximum poly density error? Thanks in advance.
  4. Y

    Doubt in MOS CAPACITOR signal connections.

    Hi, Please help me in finding the answer for the below question Out of CLK and BIAS signal, which one you will connect to the top and bottom plate of the MOS cap and why?' Thanks in advance.
  5. Y

    PVS rules for gpdk180nm

    Hi, I want PVS rule dec for GPDK180nm such as pvlLVS.rul, pvlDRC.rul, pvlFILL.rul, pvlAnt.rul, extview.rul, pvs_control_file, techRuleSets and pvtech.lib for DRC and LVS purpose. Can anybody help me with the above files? Where can I find them? If anybody has any of the above files, please...
  6. Y

    doubt in interdigitization matching

    Hi all, Can anybody please tell me how the 3 transistors of multiples 4, 12, 4 are matched? can we match in this way ABBBCCBBBA CBBBAABBBC OR BABBCCBBAB BABBCCBBAB OR...
  7. Y

    RESISTIVITY orders of layers

    Hi all, i know that the resistivity orders of layers are as follows: N well(highest) -> diffusion -> poly -> M1 -> M2 -> M3 ....... but i want to know where does "gate oxide" and "substrate" fits in list. thanks in advance.
  8. Y

    problem in common centroid matching

    Hi all, I am trying to do the common centroid matching for transistors in the diff. pair (each transistor has W=12u, L=3u, Multipliers = 12). What is the better common centroid matching? A B B A A B B A B A A B B A A B A B B A A B B A OR A B A B A B B A B A B A A B A B A...
  9. Y

    Doubt in deep nwell structure

    (this quote is taken from the thread with title " DEEP nwell for negative voltages") In the above mentioned quote Mr. Vivek has said about digital circuits dump minority charge carriers in the sub. Can anyone please eloborate on this? Thanks
  10. Y

    half cell matching in analog layouts

    thanks for your reply.
  11. Y

    half cell matching in analog layouts

    thanks for your reply. While searching some document in the net regarding half cell matching we found out that it is also called by the name "symmetric placement". Can you please elaborate on the same?
  12. Y

    half cell matching in analog layouts

    Somebody told me in analog layout apart from common centroid and inter digitization there is another type of matching called half cell matching. can any one give some information about half cell matching in analog layouts? thanks in advance...
  13. Y

    TSMC 65 nm PDK install problem

    Re: TSMC 65 nm PDK Is the PDK file for 65nm technology available for download ? Where did you get it ? If you have it, can you please share it ?
  14. Y

    Re: pdk of 180nm for cygwin

    Re: pdk of 180nm for cygwin We are using cadence virtuoso (icfb) for layout design for which we would be requiring pdk or gpdk.
  15. Y

    Re: pdk of 180nm for cygwin

    Re: pdk of 180nm(from tsmc) for cygwin hi, Currently i have installed cygwin into my computer. But i do not have any pdk. Where can i get a suitable pdk from tsmc.
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