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Recent content by Yaro

  1. Y

    Emulation of a microcontrollers on an FPGA

    I forgot to specify for an opensource code, I found different soft cores from FPGA producers, but most of them are not editable.
  2. Y

    Emulation of a microcontrollers on an FPGA

    Hi all, I've a question about possibility to emulate small microcontrollers on fpga. I place this question becouse sometimes I find C codes that are really complex and difficult to convert them to VHDL code. If there is possibility to emulate a microprocessor or a part of it inside an FPGA that...
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    Gray counter code error

    Thank you. Now I can synthesize it. But now I've an additional error when I simulate it: # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 3617300 ps Iteration: 2 Instance: aFifo_0/GrayCounter_pWr # ** Warning: There is an...
  4. Y

    Gray counter code error

    I've found a Gray Couter code already written for a FIFO code. But it gives me an error. Here's the code: ---------------------------------------- -- Function : Code Gray counter. -- Coder : Alex Claros F. -- Date : 15/May/2005. -- Translator : Alexander H Pham (VHDL)...
  5. Y

    Async FIFO 2 Clock code advice - VHDL

    Can someone advice me an already written Asynchronous FIFO (2 Clock FIFO) code in VHDL, possibly already used without problems? All the codes I've found generate me some errors. My FPGA manufacturer FIFO's when I try to read and write at the same time it create me problems in simulation and...
  6. Y

    Timing costraints, how to write an sdc file

    Since all blocks are driven by same clock GLA, when I use 50Mhz PLL I have this kind of error as you see above. When I try with 100Mhz, that is the frequency I should use, I have in addition this kind of error when I simulate compiled code: ** Warning: */IOPAD_TRI PULSE WIDTH High VIOLATION ON...
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    Timing costraints, how to write an sdc file

    Hi all, I've found problems in my code with timings. Two examples: The fourth signal should go low before fifth signal and this cause errors on first and second signals that should go to low. I have a huge timing delay in data changing when signal goes high. Would be good to reduce it...
  8. Y

    VHDL power sequencer

    In this case(updated code) I've used two gated clocks? First is StopCount and second is ModuleEN, right? But how I can stop counting? For example if I use an integer, when I reach last case and I don't need to count further and counter reach it's maximum value, what happen? Something like...
  9. Y

    VHDL power sequencer

    I've done some change to see if it was counter size problem, clock speed, counter running without EN(also added a library) and counter reset and I've tryed this code: library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PowerSeq is port ( RESET ...
  10. Y

    VHDL power sequencer

    I'm trying to create a power sequencer in VHDL, this is my code: library IEEE; use IEEE.std_logic_1164.all; entity PowerSeq is port ( RESET : out std_logic; POWER : out std_logic; EN : out std_logic; CLOCK : out std_logic; SERIAL...
  11. Y

    H 264 compression video

    Hi all, I'm looking for a chip to compress 720p/1080p raw video from my image sensor to h264 codec. In particular i'm looking for a Soc circuit easy to implement with my mcu. I've found a lot of products using fpga processors. But i don't really want use them becouse are a lot complex and long...
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