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Recent content by yanshangzhao

  1. Y

    [Moved]: Mismatch between expected and simulated patterns in scan serial

    Read simulation log and find the violation line
  2. Y

    Unable to connect scan chains in rtl compiler even though there is no dft violation

    Can you attach the content in "dft.txt"?
  3. Y

    Removing set up and hold violaions at RTL level

    Hi biju4u90, Pay attention to the logic level of big combitional logic can reduce set up violation. Hold violation is easy to fixed in PR stages.
  4. Y

    Unable to connect scan chains in rtl compiler even though there is no dft violation

    hi, what's the feedbck after you use "check_dft_rules" command?
  5. Y

    false path and multi cycle path example codes

    I think the logic that use ff_1 or ff_2 have a multi-cycle path. Because ff_1 and ff_2 's feed in logic change every cycle.
  6. Y

    about x-prapagation of double flop during gate simulation

    It's possible to see x even if you use two FF. You should think yousefl as a simulator, when timing violation happens, a register's value is x. Then x will prapagation to second FF then some part of circuit. So you can always see x in asynchronous circuit simulation no matter how many FF you...
  7. Y

    optimum design: FIFO or shift register

    Hi, This is my opinions: Area: Shift register is better, it doesn't read/write pointer Timing: Shift register is better, there isn't any combitional logic Power: Not sure, even though shift register maybe have a lot of change on bits, but FIFO has more area to implement address&mux, that will...
  8. Y

    Question on DFT - scan insertion

    Adding what I think 1. design a method to enter DFT mode 2. If there are some analog circuit, make sure all the signal send to analog are suitable when chip is in dft mode
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