Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by yannik33

  1. Y

    Calculation decay time constant (tau) for distributed capacitence

    Isn't this actually supperposotion? And doesn't suppre posotion only work for linear circuit elementrs? My aim is to to understand the influence of the channel resistence on the decay time constant for an long channel (L/W = 100/2) MOS-Cap.
  2. Y

    Calculation decay time constant (tau) for distributed capacitence

    What's an approach to calaculate or approximate the time constant for the distributed RC-Network as given below?
  3. Y

    Flatband voltage of an technology

    I tried to find the flatband voltage of the technology I use in the documentation of the technology (ibm 130nm) but it seems that this information is not provided -- is there a way to get the neceassary information somewhere (spice files)?
  4. Y

    CMOS dopinf of substrate and nwell

    CMOS doping of substrate and nwell Would a NMOS work if the substrat ist p+ dopted and the nwell of the pmos n+? What's the reason it's n- (ie less dopted than the contacts)?
  5. Y

    VLSI: active and n+/p+

    Why differentiate VLSI-Systems between active and n+ resp. p+ ? If the p+ region is larger doesn't this increase the likelihood of an short circuit between drain and source (eg in the figure below there is a connection between drain and source side doesn't this lead to a short circuit?)...
  6. Y

    PMOS radiation hardness?

    **broken link removed** Why does the radiation and the creation of positive charged charges not change the potential of the n-substrate?
  7. Y

    PMOS radiation hardness?

    Why are PMOS-Transistor more insesetive against radiation?
  8. Y

    shunt peaking and current mode logic

    Most books and articles explain shuntpeaking/inductive peaking for an CML circuits with loads connected to vdd - is there a way to use this technique for loads connected to gnd? (like in picture a.)
  9. Y

    [SOLVED] active inductor and slew rate

    How does an active inductor (see Fig.) improve the slew-rate of a signal? In the s-domain the transfer function possess an additional zero and pole but it'd be really kind if you could explain it to me in a way more related to the actual components. Isn't the idea that for an large di/dt (i.e...
  10. Y

    Differential pair -- VSource

    How can I calculate the source voltage of a differential pair? Esp the commen-mode voltage V_{S0} as shown in the pic? Thanks
  11. Y

    Normal NMOS as Capacitor

    Is it possible to use a normal NMOS Transistor as a Capacitor (because *NMOS Varactor (e.g. n-diffusion in n-well) *Inversion type MOS varactor aren't normal NMOS Transistor), i.e. between Gate and Source/Drain? Quite anumber of pages show the characteristic of the GateBulk-Capacity vs. Ugs...
  12. Y

    Current Mirror with Cascode

    What's the difference to the simple current mirror? Respectively why is the performance of the circuit that includes the cascode into the diode connected mos so much better incomparision to the normal current mirror?
  13. Y

    Current Mirror with Cascode

    Sry, My mistake. That's the correct circuit.
  14. Y

    Current Mirror with Cascode

    What's the difference between both current mirror with cascode and how does the circuit on the right side work, thx?
  15. Y

    cycle time, slew and slack

    I read that it is possible to use the slew rate in combination with the slack of the following FF to "stretch" the cycle time of the logic before the FF. (On side affect is the reduction of the slack of the following FF). How does this work and what's the name of this effect? thanks allot
See more

Part and Inventory Search

Back
Top