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Recent content by yaju1984

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    [SOLVED] gpdk180 RCX error, No cellview for pcapacitor found

    Hi, I am doing amplifier design in Cadence vituoso and am using gpdk180 library my schematic and layout are complete, DRC and LVS successful, but when i try to extraxt(Run RCX) i get the error "No cellview for pcapacitor found" There are no paracitic components in gpdk180, how can i extract...
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    [SOLVED] channel length modulation parameter for gpdk180 cadence

    hi i'm designing a three stage operational amplifier, and am using cadence virtusoe for schematic and layout i am using the gpdk 180 library for this design i need to find out the channel length modulation parameter 'Lambda (λ)' for this library can anybody guide me as to whether it can be done...
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    [SOLVED] VLSI design project ideas for final year

    Thanks Guys I'm Looking into the Ideas You suggested Any Ideas in Analog Design? The project should preferrably last for one whole year.
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    [SOLVED] VLSI design project ideas for final year

    Hi I am studying Mtech VLSI design, and am in my final year. I am searching for project topics for my final project. Can anybody suggest any IEEE projects, or any other project ideas? I am interested in Digital design, VHDL, Verilog. Any help will be apreciated.
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