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Recent content by y7wu

  1. Y

    intrinsic gain of mos. Help Pleeeease.

    Thank you for this info. It helped me also
  2. Y

    foster's reactance theorem disproven?

    Can you provide some reference that claims metamaterial can rotate counter clockwise on the smith chart? If this were true, wouldnt the gain-bandwidth constraint be gone as you can now perfectly conjugate match a set of impedances on the smith chart? I have a hard time linking the "negative...
  3. Y

    How close to the edge of the smith chart can you get ?

    s22 in smith chart Hi all, Thank you for your response. Fvm: Class F PA requires the odd harmonics to be terminated with open circuit and even harmonics with short circuit in order to achieve square wave voltage and half sine-wave current which yields high drain efficiency. Element_115...
  4. Y

    How close to the edge of the smith chart can you get ?

    loss tangent smith chart Hi, I have been designing a Class F amplifier with harmonic output matching network. The output matching is done on a Rogers RT/duroid 5870/5880 substrate, which according to the datasheet has a loss tangent of 0.0005 at 1Mhz and 0.00012 at 10GHz. I entered the...
  5. Y

    Why is the Vth negative in RF PA?

    Re: Why is Vth negative? Hi, Thank you for letting me know about depletion MOS. I've only dealt with enhancement MOS before. At low frequency we're taught that with high impedance probe we are able to observe voltage waveform without loading the circuit. I'm speculating that high impedance...
  6. Y

    Why is the Vth negative in RF PA?

    Why is Vth negative? Hi there, I'm a student working on power amplifiers designs who just started recently on master. I've had some background in analog IC in my undergraduate courses. but I have some question about the FETs used in RF PA that are puzzling to me One of the question I have is...
  7. Y

    phase noise in dBc/Hz greater than 0dB???

    phase noise positive dbc/hz Just as a correction, In Pnoise the negative output node is selected to be GND, not n9_0_0 (n9_0_0 and n9_0_1) are the differential output of the last stage. Added after 47 minutes: I believe think this answers my question
  8. Y

    phase noise in dBc/Hz greater than 0dB???

    how much phase at 0db Hi all, I'm simulating a differential ring oscillator with 10 stages in cadence I'm using PSS to determine oscillation frequency then Pnoise to get the phase noise. I seem to be getting some very strange results where the phase noise has positive dBc/Hz from relative...
  9. Y

    How do I generate a 50Mhz clock on Altera Stratix II

    Hi there, I turned off the other outputs and indeed the waveform improved! I really must thank you for walking me through the debugging process. I believe I have a usable square wave. To answer your question echo47, the FPGA and the output connector are separated by about 2 inches. I'm...
  10. Y

    How do I generate a 50Mhz clock on Altera Stratix II

    The oscilloscope bandwidth is 500Mhz, (Agilent MSO6054A with 4GS/s). There is no external trace, i.e the probe is directly connected to the output pin of the board. the probe cable length is 1.5m IO-standard is 3.3V (LVTTL), current strength is unknown (is this something I can assign in...
  11. Y

    How do I generate a 50Mhz clock on Altera Stratix II

    stratix ii high frequency sine Hi there, We're trying to generate a 50Mhz square wave clock on the Altera Stratix II to send to an off-board chip. The way we're doing this right now is using the on board 100Mhz crystal oscillator and implementing using the following VHDL block. where in_clk...
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