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Recent content by Y.SAI SARASWATHI

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    How is voice communication through internet different from mobile communications

    Thank you, Are all the techniques for enabling communication between 2 computers same as that of mobile communication except that signalling process that you have mentioned. Unlike phone calls they need to take long way and require permissions from many interlinked servers then how is live...
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    How is voice communication through internet different from mobile communications

    Hello, I am new to computer networks, help me out in understand this. Both audio and video communication are possible through many internet protocols, how they are different from mobile phone communication. In mobile communication I could see many antennas all the way which helps to establish...
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    when can we use Flip flops to design Binary adder ?

    Hello, Combinational circuits can be realized using sequential blocks, similar to truth table in combinational design, use state transition tables and then design input equations for each flip flop using corresponding excitation tables of flip flops. if required use control inputs of each flip...
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    VHDL for Real time applications

    Hello, I am in search of concept or any application that I can implement on FPGA using VHDL. Can any one suggest me some real time applications i,e vlsi project that can work as an embedded system i,e it should not be like implementation of iir/fir filter on FPGA. It can also be related to any...
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    VHDL Synthesis Code help

    I need to give conv_start only for 15ns after rising_edge(clk) how to write in synthesis
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    VHDL Synthesis Code help

    I have modified my code this way It has not given those warnings. will this work good after dumping into FPGA. What is the difference in using rising_edge function and clk'event and clk='1' Can I ignore the warning WARNING:Xst:646 - Signal <diff<11:4>> is assigned but never used.
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    VHDL Simulators need help

    I have changed the run time but it is not responding I have seen features of active hdl 6.1 ,they have mentioned that maximum simulation time is 10.1us. Please tell any other tools that are available online.I need to run it soon.
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    VHDL Synthesis Code help

    Hello, I am using xilinx ISE 10.1, following is the code snippet. It is not showing any errors but it is taking read,cs_adc as logic '1' always. It is displaying following warnings My design is when adc gives active low eoc ,after that when it returns again to logic'1' then we should send...
  9. Y

    VHDL Simulators need help

    Hello, I am using Active HDL 6.1 simulator. In that I can only upto 10us but my design requires a minimum of 17 us. Are there any simulation tools that supports supports 32us run time that are available online. Thank you.
  10. Y

    VHDL Synthesis Code help ,required clarification.

    Thank you every one, I require one more clarification regarding usage of those fixed point numbers. If I wish to implement multiplier and accumulator logic like I have mentioned in the first post where all coefficients(a1,a2,.....) are fixed point numbers. Can I simply write code using FOR LOOP...
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    VHDL Synthesis Code help ,required clarification.

    I require fixed point logic,actually I am new to work with FPGA's. Are there any Packages related to synthesis in xilinks ise, so that we can directly work with fixed point numbers Thank you,
  12. Y

    VHDL Synthesis Code help ,required clarification.

    Sorry, that I have mentioned in that way. But why I have mentioned is , even for the last two posts I could not find any relevant reply. I will not repeat it again.
  13. Y

    VHDL Synthesis Code help ,required clarification.

    Hello, I am working on a project related to implementation on FPGA using VHDL coding. At first i do not know that real data type will not work for synthesis. Now I need to perform a function like Y=(a1*x1+a2*x1+.........+a8*x8) where (a1,a2....) and (x1,x2,....) are real numbers(with decimal...
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    Fixed Coefficient Predictor Design for DPCM

    Hello, Please tell me how to calculate Coefficients(Weights) of fixed Linear predictor to be used in DPCM(Differential Pulse Code Modulation). Will fixed Linear Predictor gives better results for coding of speech signals. Thank you.
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    Will FPGA takes real time speech signal as input?

    Ok,but I want an ADC whose output is 11.001100110011... in order to interface it to fpga. Can you suggest me some Ics with that much good precision.
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