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Hi all,
I'm designing layout for CMOS RF power amplifier.
And I'm wondering is it compulsory to add RF pads in analog circuit design? can we ignore adding RF pad?
If didn't add RF pads, what are the reasons or another way to prove my layout is good enough?
Could someone please advise? Thanks.
Hi,
I've changed smaller step size, but the PAE curve still didn't have much changes. But this time, my question is the x-axis (Pin), I need to get maximum PAE which stay at Pin> 0dBm.
Hi,
I had designed a CMOS Power Amplifier using Cadence. Attached is my simulated PAE graph, from the graph can see that the maximum PAE is not met at Pin> 0dBm. Is it any suggestion to solve it? Thanks.
Hi,
I'm using Cadence to designed a CMOS power amplifier and I've simulated PAE, but the graph didn't perform a smooth curve. May I know how to setting so that the curve can be plotted more smooth?
Thanks in advance.
Hi,
I've designed a CMOS power amplifier. I'm unable to simulate PAE graph, I've chosen all the ports, but the bottom part of the direct plot form shows ERROR: /PORT1/PLUS is not a kept output. May I know what is the error means?
Thanks.
**broken link removed**
I had ran transient analysis at each node, but the result came out is blank. May I know which part got problem? Can you advise me please? Thanks
Can you provide the link or manual regarding steps to check the node voltages and branch currents?
Hi,
I had designed a CMOS Power Amplifier using two stage class E topology. May I know why my PAE simulation result didn't have saturation point?
When I tried to check the transistor work or not by simulating dc analysis, but the IV graph comes out is blank. I also tried to run dc analysis on...
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