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Recent content by xuxia

  1. X

    How to set debu$$fsdb reader version?

    this fsdb file has higher version please upgrade your software, or you can use the same version to dump fsdb.
  2. X

    Need description of Verdi shorcuts

    Verdi shorcuts you can find some "*.menu" file in /etc. in these files,you will find "key" session, all bind key are defined in the session
  3. X

    How to simulate a SystemC design with Cadence NCsim?

    ncsim systemc please use ncsc
  4. X

    what's difference between code coverage and function coverag

    as title, ths!
  5. X

    What exactly is the clock jitter?

    highfrequencyelectronics.com jitter part 2 difference between real clock and ideal.
  6. X

    what is "zero time glitch"?

    zero time glitch In RTL ,why create "zero-time" glitch? tks
  7. X

    [Question] Debussy error message

    which version which you are using? from your information ,this should be a bug and was resolved in high version
  8. X

    What's your opinion on CAD tools for Windows/Linux OS?

    Cad tools most eda ventor provide the eda tools for AMD64bit linux os .the benchmark is better on the AMD64bit platform than sun.
  9. X

    What are the difference between ASIC Verifation and Test?

    before phsical implemetation,is verification.after implemetation,is test
  10. X

    Verdi Training with labs for your best

    how to track a signal using verdi for tracing unknow in gateleve, verdi is the best choice. one unknown issue in my design ,I spent one week to find the source by using debussy ,but using verdi ,only spend three hours.
  11. X

    lint tools for verilog

    nlint download free spyglass is best. nlint is also good.leda's advantage is full integreted in sysnopsys design flow.for blacktie ,I have no ideal.
  12. X

    CTS & optimized clock tree

    astro clock tree optimization why some skew is usefule?please give me an example,tks!
  13. X

    Virtuoso Layout Editor VS. Virtuosu XL Layout Editor

    virtuoso xl layout editor virtuoso xl is so hard to start.and the layout hierachy must match the circuit .It drive my layout size is so huge.
  14. X

    Laker problem with allocating 64 color cells

    EDA(Laker) Question? in laker_install_path/etc/default.dsp file ,all color definiton are included in it. I think you can remove the enviroment variable and laker will use the default display file automatically.
  15. X

    What is the DVE of VCS7.2 for ?

    What's DVE of vcs7.2? anyone can tell me what's for of the prodcuts?
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