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Hello,
I encountered a error when I use synplify preimier to synthesis a VHDL design.
the log is
@E: CD505 :"/filepath/file1.vhd:497:30:497:36|type:Expecting enumeration literal
1 error parsing file /filepath/file1.vhd
and the code in this file1.vhd is:
497 type start is (INIT, DEFAULT...
hi guys,
when I use Mentor mbistarchitect to generate the bist for memorys, a problem occurs, the log is shown below:
// ...
// ** Successfully added BIST circuitry.
// command: save bist -verilog -script -replace
Saving MBIST Data:
Saved ./xxx.v
Saved ./xxx
....
// command...
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