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i don't get much of what is stated there.
but what i have found is i can read number of reserved sector from PBR and add to LBA of partition to get starting address of FAT.
is that right??
---------- Post added at 23:02 ---------- Previous post was at 22:46 ----------
ok i got it..
thanks,
okay now i got partition boot record but it doesn't specify starting address of FAT. how to get to fat from here??
h**p://home.teleport.com/~brainy/fat32.htm
i am assuming the link given has correct partition boot record.
hi,
i want to read the file allocation table inside SD card but i cannot figure out the address where it is??
i know that MBR is at address 0 (logical) but how to find where is FAT??
hi,
i really don't know how to do matlab but anyways i wanted to write a matlab code.
i created a structure to store RGB images from a video using
mov(1:nFrames) = struct('cdata', zeros(vidHeight, vidWidth, 3, 'uint8'), 'colormap', []);
now i am having trouble in creating a structure for...
ok i get it.
but if hsize is 256 bits and our bus width is 32 bits then we have to divide our transfer to 8 blocks for one beat.is that right??
also according to arm document i assume when it talks about transfer it has a 8 bit wide memory. is it true??
thanks man for the reply.
really appreciated.
but my confusion is really basic. how are HSIZE and HBURST related?
if i try to send 8 bit wrapping from a memory interfaced with master what will happen??
can anyone explain me what happens in 4-8-16 beat transfer. i mean i have read the documents but i dont understand what happens in memory.
can someone explain how it take place with help if memory? :oops:
I wrote this small code to test the values stored in a 2-d array but it is not simulated by VCS. can anyone help??
i am new guy so please point in a specific direction.
module xyz();
reg [31:0] addrmem [31:0]
for ( i=0 ; i<33 ; i++)
begin
addrmem[i] = $random();
end
endmodule
hi,
i have never worked on FPGA's but i have a slight idea of what they are by reading on web. so please consider me a lay man as you explain.
can we store data on FPGA from an external device and carry it somewhere else??
for example if 2 fpga's are connected and data is send by one to other...
thanks guys for the reply but the problem is i have to swap this way only but i am not able to figure out how to declare "word".
maybe something to do with tristate but i am not sure what to do??
@lostinxlation
ya i didn't think of the circuit i was just trying to run the code here...
hi i am trying this swap code
i define "word" as it will be input and output both but now i cannot define it as "reg" and also there comes an error in swap instruction.
is there any way around it??
i know trying input and output for "word" didn't help.
module swap(clock,word);
input clock...
so you mean that
alway @ (posedge clk)
..<--- a statement 1
@(posedge clk)
..<--- a statement 2
@(posedge clk)
if we consider 1 posedge and 0 negedge
for every 1--- statement 1 excute
for every 101 ---statement 2 execute
hi,
i was trying a nested always statements.
always @ (posedge var1)
begin
..
..
..
@ (posedge var2)
begin
..
..
..
end
end
now i don't know if this is correct or not but the compiler doesn't step even into the first always block.
can anyone explains how does these nested always work
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