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So i finally finished what ive been doing :-D :-D
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I've added a 3rd input in "aktivnidisleji" and changed from "OR" logic gates to 3-input "AND" gates, so when the frequency divider send logic "1" "aktivnidispleji" will activate and send 4 bits on AN3,AN2,AN1,AN0...
Uhm i dont know how to explain. For example, if you want only 1st display to work you have to put 3 others in logic "0" to be off. If you dont, all 4 displays will be on. BUT, there is pin for each display so you can control only 1 if you want to. I dont know if i explained right xD
And ive...
Yea, i dont need mux, i need demux :-D. Finally ive made it:
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Now i need to do some K-maping to calculate 4 active displays, and thats it i think. :-D
There are 4 7-seg displays on the FPG-a. Although they are all connected (if i want to write a number only on first one, i have to turn off 3 out of 4 displays), there are 4 control lines (1 for each display, AN3, AN2, AN1 and AN0).
Im not sure if i understand 2nd paragraph about "slices" xD. Well, anyway, proffessor told me i should do it this way , although he told me it should work with an counter too. I havent done 2-to-7 demux yet, so i dont know if there will be some problems about connecting everything together...
So far i made 2 bit counter that would count those 4 states, using T flip-flops with activation on falling edge:
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and frequency divider, which will divide 50MHz clock by 26 times. Which means that on output (CLK_OUT, although i dont know if you can see it on the picture)...
Uhm, proffesor told me i will need freq divider, which will divide that 50 MHz 25 times ( with 25 flip-flops, i was thinking i could use flip-flops which are active on rising edge of clock , so when 50Mhz pass through 25 of them , output signal would be 1.49 Hz which is kinda similar to 2...
Yesterday i sent e-mail to my mentor, asking him about the assignment. He answered me that i will need this : frequency divider by 1.49 Hz, 2-to-7 decoder and a 2 bit counter which would count 4 states (00,01,10,11), and depending on which state is active that letter will be shown. So, when 00...
Thank you for your reply Barry.
Yep, unfortunately, i have to do this project with a schematic. And yes it does make sense :-D. Ok, well i guess i will make custom simbol for 27-bit counter in Xilinx, and then ill make scheme for 7-segment displays. I'm currently working on this so i will try...
Hello everyone. I would like to excuse myself in the beginning for my bad english.
I got assignment to draw a scheme of circuit in Xilinx on Spartan 3 FPGA board, that would write a word on 4 7-segment display , and it needs to blink every 2 seconds. The word is "radi" which means "IT WORKS"...
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