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Recent content by xjxmn

  1. X

    Questions about RFIC design using LC folded inductor source

    Help for my design What do NF and OIP mean? Added after 1 minutes: Can you provide your topology and some schematic?
  2. X

    Problem about BNC cable

    bnc cabling problem I want very high SNR signal source. Signal gererator generate the signal , The signal travell through the BNC cable to my circuit. How can I transfer the single ended signal to differential ended signal with balanced input impedence. Transformer is a choice, but I need low...
  3. X

    need u help on this current limiting analysis

    need u help on this current limit analysis I have ever designed LDO by using a scaled down PMOS to sense the current not resistor to sense it. The sensing pmos monitor the gate of pass pmos to get the ratio current of loading current. I haven't seen the current sense of your circuit.
  4. X

    need u help on this current limiting analysis

    need u help on this current limit analysis There is no sense of current , how can you limit it ?
  5. X

    How to test uV level offset of opamp?

    50uV, which point do you refer to. Why not filter power first or you can use a high performance power supply. You can get rid of the noise in power supply. The problem is, what's your noise level of OA, whether it exceed your offset, if yes, you should watch is it in high frequency or low...
  6. X

    How to measure the Gm of an OTA in Cadence?

    OTA TestBench Maybe you can do DC analysis in Candence , and you can view the parameter, So can calculate your Gm of OTA.
  7. X

    need u help on this current limiting analysis

    need u help on this current limit analysis Let me try Added after 24 minutes: When Vo<0.8, what is Vref and Vss? What do A B C D connect to?
  8. X

    About noise cancellation

    Which frequency range do you care? I think you need to control the Equivalent intput Noise (RMS) to <=11uV, not output noise. Large input transistor size, or chopper.
  9. X

    Class AB OPA AC Analysis ??

    From the gain plot of 5V, I can calculate the phase margin. PM=180-90-arctg(0.1)+arctg(0.01)=84.6 arctg(0.1) for the contribution of second pole, arctg(0.01) for zero. I think the poor gain is because the cascode transistor works in linear region, in 5V condition. Because both 3V and 5V have...
  10. X

    Why the tail resistor can increase the amp's stability

    I agree with n1cm0c, RTL range from zero to infinite, gm will decrease, and the main pole almost not changed with RTL, so the phase margin will increase, the system will be more stable. But why not use miller compensation to stablize the OA. What's the advantage of this structure?
  11. X

    What should I care in the layout of low noise PCB.

    I want to get micro volts level noise in one pin, what should I pay attention to. The power is dirty. Anyone can help me , please.
  12. X

    Class AB OPA AC Analysis ??

    There's no problem in your circuit, I think you can try another tool to simulate AC respose. Maybe it's just a bug in your tool. And you can try other different Vdd in your tool.
  13. X

    Low Dropout (LDO) Regulator Design

    regulator design Can you explain it for me? Thanks.
  14. X

    how to remove the pole in the Gm&#65281;

    Can you describe your question in detail ?

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