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Hi everyone,
I have a problem submiting VCS simulation jobs through Condor. I have 120 simulation executables, and each of them runs well by the command ./simv. However, when I use condor to submit them, I got the following error message:
Error-[UCLI-026] Tool type problem
Internal error...
Hi everyone,
When I was using HSIM/VCS to compile a Verilog-SPICE design, I got a compilation error.
The error message is as follows:
Error-[UPIMI-E] Undefined port in module instantiation
fpu_add_flat_nc.v, 6620
Port "QN" is not defined in module 'DFFX1' defined in "saed90nm.cdl", 2019...
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