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Recent content by xin

  1. X

    how to generate stair output of flash adc

    in ahdlLib, there are ideal dacs in veriloga view
  2. X

    What does Mirrors stands for in analog design?

    Re: Mirrors maybe you can refer ro the berkeley 240, Lecture 05
  3. X

    How to increase or decrease slew rate of an op amp?

    slew rate boost amplifier increase or decrease the output stage current
  4. X

    Generating the bias voltage of an op-amp

    Re: Bandgap Reference Normally current mirror is used to bias the opamp. The current in current mirror is often generated from bangbap with a feedback network.
  5. X

    how to simulate capacitor mismatch of a pipeline SH circuit?

    Re: how to simulate capacitor mismatch of a pipeline SH circ if this mismatch comes from process variation, post layout simulation can not give you help on this mismatch effect. I always calculate manully. you could get a mismatch report from foundry and use sigma data to calculate

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