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Hi, i am trying to convert verilog code to vhdl, however i have some problem face at this part. Would like to double check it if i convert it correctly.
assign oREAD_SDRAM_EN
= ((x_cnt>Hsync_Blank-2)&& //214
(x_cnt<(H_LINE-Hsync_Front_Porch-1))&& //1015
(y_cnt>(Vertical_Back_Porch-1))&& //...
This is the vhdl code I had, I am not sure how write a test bench for it. Anyone able to guide me through this?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity ltp_controller is
port (
iCLK: in std_logic; -- LCD...
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