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Hi,there! Recently I have been working on the design of inductor. My method is, first drawing an inductor in Cadence Virtuoso, and then getting its characteristics in ADS after import.
To verify the validity of my ADS simulation method, I'd like to compare the foundry model（simulated in...
Hi, I got a TX and a RX now, on 2 PCBs, between which I want to establish communication. The problem is, first I only have one pair of differential clock from the clock generator, but both of TX and RX need one.Also, I think they need same-frequency clock to work properly, so using 2 different...
I've designed a PAM4-Transmitter with a Nyquist-frequency of 10GHz.Its test result came out far from expected.Apart from the IC itself,I use S-parameters module to act as a low-pass filter to get a general influence of PCB traces&Cables&Connectors in the design process.
Even so,the outcome is...
Re: How can I evaluate on-chip bypass-capacitor's capacity based on the topology?
It also seems to me that the inductance is large because of the loop,but how can I estimate it?
Re: How can I evaluate on-chip bypass-capacitor's capacity based on the topology?
I use off-chip capacitor as well on the PCB.Is there any problem with this on-chip one?
The transmitter I designed has been showing lots of jitter.I think there's something wrong with the layout topology.Pad of the power supply is a little far away from the circuits by connection through thin metals,thus producing a resistance as large as 2 ohms,which would lead to IR-Drop.It...
1)Can those rise/fall edges be so asymmetrical now that I've keep the N:P ratio relatively reasonable?And from Spectre,the edge-rate seems perfectly matched.Also,I can understand the problem if the chain is single-ended,but these are differential clocks between which I put some cross-coupled...
Since I have used the same clock generator to trigger another TX,which shows little overall jitter,I believe the jitter mostly doesn't come from the test setup itself,so I can focus more on some on-chip factors like IR Drop or Ldi/dt Noise.
The pic in #3 shows the TX output when data input is...
I have been recently working on a PAM4 transmitter with its output having duty cycle distortion.In theory,its duty-cycle accords with the high-frequency clock's generating it.Since that clock only comes from an external clock going through a CML2CMOS converter and a series of CMOS buffers(over...
I've recently designed a wireline transmitter,but it turns out to have so much jitter.Since I can make sure that the clock generator is relatively clean,I think the noise most probably comes from some on-chip mechanism like IR-drop or inductor-induced jitter.So is there any way to approximate...
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