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I am designing a multistage multirate system. it has 4 stages. all of them share the same main clk. the filter stage's operation frequency is clk, the second stage's operation frequency is 8 times smaller than clk. so I design a counter in the stage 1. every 8th clk period, the stage 2 get a...
Hi all
my paralell output signal frequency is 48khz, its width is 24 bits. it has to be converted into serial signal. what my question is how to design a paralell to serial module with verilog. Maybe I can realize it with FSM or a sinple shift-register. which one is better. and the...
I have a question about the out of the sigma-delta modulator. I read some references about the sigma-delta ADC. They say there need a high pass filer in the digital decimation filter in the ADC to reject the DC offset. But I don't know where the DC offset come from, and how to reject it. Is a...
I am studying a digital filter(used in a sigma-delta ADC). It is a multistage filter. I use the FDATool in matlab to generate the code of all the filter. And then I use the modelsim to simulate. But I can't understand the result(it looks like it will always increase(positive and negative...
Hi,all
I just design a half-band filter in the matlab for elimatate the outband noise and decimate at a factor of 2.What the matlab generate is a Direct-Form polyphase FIR. I don't kown how the polyphase FIR work. What is the difference between it and the Direct-Form FIR. Is the frequency...
designing cic filter in matlab
the frequency response is determined by the R(decimation facor),N(the order of the CIC) and the M (defferential delay). the passband is determined by them~~~
is the passband edge is the at the -3dB ?
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