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Recent content by wowo1215

  1. W

    High speed USB 2.0 eye pattern violation

    Have you try test the impendance of the whole D+/D- loop? Maybe the impendance does not keep continual.
  2. W

    voltage problem in my PCB

    The first thing I can suggest is you must post some related information, like the schematic and layout, then you can get some useful analysis soon. Another thing you can do is what cameo_2007 said. or just do the opposite like i usually did.
  3. W

    Help designing Buck Converter in PSpice

    And u must also pay more attention to the working mode of MOSFET,what we want is switch, not a resistor,right?
  4. W

    Help designing Buck Converter in PSpice

    Yes,just do as atripathi told you!
  5. W

    Increasing/decreasing the rise time of signal on differential trace

    Re: increase Rise time I am not very sure why you want to increase rather than decrease the rise time.But if you really want to, then some basic troubles in signal integrity maybe really give you some help.(sounds really ridiculous)
  6. W

    regarding simulating chips using PSPICE

    In my experience, u can get a IC's IBIS model or encrypted Hspice model from the vendor, but I am not sure you can get accurate result with these models since they are much oriented to functional simulation rather than power consumption feature.
  7. W

    Who use Allegro PCB 15.7. I need small help ( will pay $10)

    Re: Who use Allegro PCB 15.7. I need small help ( will pay $ I really want to give u a hand,but unfortunately I only have a 16.0.
  8. W

    what is 'transient response'?

    Thanks,FvM. So any suggestion to improve it? It seems to be related with phase/gain of the control loop,but I really have no idea on what's the relationship between them.
  9. W

    what is 'transient response'?

    Hi All, I am a newbie on buck converter. By now, I know the transient response is the performence related to dynamic load, but what is this phase exactly mean? And how to improve it? Thanks.
  10. W

    the race in digital circuit

    Thanks, Sharon. I know what cause a race,but the question is: why the method indicated can avoid race?
  11. W

    the race in digital circuit

    Hi All, Anybody can help me to explain the sentence below, why this config can lead to race-free operation? Thanks. "To ensure race-free operation, changes on TAP inputs (TMS and TDI) are clocked into the test logic defined by this standard on the rising edge of TCK while changes at the TAP...
  12. W

    IBIS-AMI model for serial link simulation

    IBIS-AMI model Hi guys, I know both Cadence and IBM have developed IBIS-AMI models for high speed serial link simulation, so anybody owned it can send me a copy? Thanks!
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