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Thank you for your reply,
However I don't know system C, I know system verilog.
Can you point me to some modeling tutorial with systemverilog or even system C ?
Hi,
I want to know how to model any hardware in ASIC. As of now I'm thinking functionality + real world timing, is that sufficient or there are more characteristics which need to be considered.
What are considerations I should follow if hardware is completely new (no datasheet -- timing info...
ok so if I understand it properly:
write a perl code to
1. search for f/f in netlist (something like DFF2x etc.)
2. replace it with muxed f/f or mux and a f/f
and thanks for the suggestion :)
Hi everyone,
I've been reading about DFT (Scan in particular). The more I read about it, I keep finding ways to insert scan chain in design with the help of synthesis tools (which is good).
However I wanted to know if that is the only way or we can insert scan chain while writing a verilog...
Thanks for the info :)
So I've been reading about getting milkyway database from lef (library exchange format) which is provided by osu libraries.
As explained in tutorial with this post read_lef in Milkyway (tool) provide me with required milkyway folders (FRAM and CEL) however I'm still...
Hi everyone,
I'm using IC compiler for placement and routing and following https://www.edaboard.com/threads/155698/ script over here or the tutorial from attached pdf file.
I'm using OSU libraries for synthesis purpose and want to continue using them for Place and Route as well.
Now as...
Hi everyone,
I'm using dc compiler to synthesize design. I can easily synthesize smaller designs but as designs grow in size dc_shell or design_vision close down with fatal error.
Is there a way to set up computer resources so that dc_shell won't fail but will take longer time? or anything...
Hi everyone,
I've pretty stupid question (maybe),
So I can design (verilog design) for specs without delays pretty well.
However when it comes to specs with delays (like memory takes 5nS to complete a write operation) and that memory is a part of larger design. I can't code it.
I would like...
So the problem is been solved. Just in case if anyone faces the same issue
Previously I was doing read_verilog design.v (read_verilog doesn't support system verilog right out of the box)
So instead the one command that worked for me was analyze -library <WORK> -format sverilog <design>.sv...
Hi everyone,
First of all thanks a lot for all previous help. I could successfully use 'ifdef and file wrapper. With dc compiler I can synthesize the design only if I'm not including logic type variables.
For one implementation of design I have to use logic type variables, compiler and...
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