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Recent content by windtutelary

  1. W

    how can I call a VHDL shared variables inside Verilog

    by use $hdl_xmr can do it, but shared variables array is VHDL declare a package, and in verilog without instance can access it ??
  2. W

    how can I call a VHDL shared variables inside Verilog

    hi all, i have a problem with VHDL and verilog mixed , now VHDL and verilog is connect success, VHDL is TOP and VHDL has a shared variables, how can I call a VHDL shared variables inside Verilog code??? Thank you
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