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Recent content by wilsons

  1. W

    Does Verilog-A support arrays assigment?

    verilog arrays Does Verilog-A support arrays assigment? Is there a method to assign an array in a single statement. For example, a<3:0>={1,0,1,0} and suppose 1,0 is a specified level. Thanks for your help!
  2. W

    NEED YOUR HELP~want to amplify a signal that is DC value

    Re: NEED YOUR HELP~ no, I need to transform the single end signal to differential signal !
  3. W

    NEED YOUR HELP~want to amplify a signal that is DC value

    Re: NEED YOUR HELP~ I want to know opamp's structure. The "DC" mean's the signal changed very slow compared the useful signal.
  4. W

    NEED YOUR HELP~want to amplify a signal that is DC value

    NEED YOUR HELP~ Hi，everybody! I got a problem now and need your help! I want to amplify an signal that it’s DC value maybe change, then I add a CAP to get the AC siganl. Next,I want to amplify that ac signal about 20dB. The output is diffrenetial, so I want to let CM level to be 0.9V. VCM is...
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