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Hello ,everyone:
I try to translant the verilog-beharioral netlist into spice-netlist using synopsys hercules.
The whole command is as follows:
nettran -verilog ../vlog/file.v -verilog-b0 VSS -verilog-b1 VDD
-cdl /export/DE_home1/caslib/smic/aci/sc-m/lvs_netlist/smic18m.cdl...
vcsad.init
In a mixed-signal simulation , how do we add stimulus in to the design ?shall we add digital/analog stimulus seperately ?
I don't know wheather what i think is right , so if anybody give me some hints , I will appreciate very much .
1.
Verilog-top
vcs files.v +ad=vcsAD.init
we can...
nanosim vcs
I don't know wheather what i think is right , so if anybody give me some hints , I will appreciate very much .
1.
Verilog-top
vcs files.v +ad=vcsAD.init
we can add digital stimulus in the verilog-top module in " initial " procesure , and in the vcsAD.init file , add this command...
Hello ,all
I met with a problem when i try to do transistor level simulation using nanosim ,it puzzled me for several days . I hope someone may help me out .
I write a very simple 4-bit full adder in verilog , and I synthesis with Synopsys DC adn get a verilog netlist .
I simulate...
vcd2vec
hello , all
I want to translate my vcd file to vec file so as to read in nanosim .
I found the vcd2vec command , vcd2vec <-d > -nvcd vcd_file <-nsig sig_file> <-nvec vec_file>
because i'm a newbie , i don't know what is the signal information file ,just found some syntax about this...
vcd2vec
Dear all
I have a digital design writen in verilog .
after synthesis, i want to simulate in the transistor level using nanosim .
and i've translate the verilog netlist into spice netlist using nettran command in hercules .
and I want to also translate the testcase written in ntb in...
I'm using the ARM7TDMI Design Simulation Module .
the sdm is integreted in a digital design , and finished the synthesis .
I meet a problem when i transtlate the verilog netlist into spice netlist .
I use nettran command in hercules to do this , for the standard cell , i have the cdl file to...
pspice vhdl tools
thx very much .
thx every body .
I use nettran in hercules .
nettran -verilog file.v -verilog-b0 vss -verilog-b1 vdd -outType spice -outName file.spi
is it the right commond ?
I've got the spice netlist . but still there is some warnings .
thx all .
when i simulate in...
verilog to spice
Dear All,
I'm trying to get Spice netlist file from Verilog/VHDL. After I
synthesized the vhdl file using DesignCompiler, what tools available that
can help me to get the spice netlist. I need the interconnect
information incorporated in the spice netlist. Any help will be...
solaris system , ic5033, ultrasim41
I want to ask , how can i integrate the ultrasim in to the ICFB's menue ?
modify the .cdsinit ??? what is the sytax then ? could anyone give a reference ?
Or could anyone tell me where can i find the answer.
I've already looked for the doc directory in the...
libcdsdoc_sh.so
I installed Ultrasim on unix .
but i don't no how to set the settings .
i use lmgrd and get the license started .
i add the path to the .cshrc as following
set path=($path /disk/eda2s/cadence/UltraSim/tools/bin )
set path=($path /disk/eda2s/cadence/UltraSim/tools/dfII/bin)...
3x a lot for ur generous help .
i untar the files and get the same directories as you .
but i don't have the file /home/wildwood/n-hnl5/nassda5.0/platform/linux_24/bin/hsim ,
it is hsimd . and , in the same dir , it has hanex , but no critic .
i use command which hsim , i get...
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