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Who has "the verilog PLI handbook"?
It's so difficult to get the e-book...
Added after 41 seconds:
Who has "the verilog PLI handbook"?
It's so difficult to get the e-book...
As a newbie for specman, it's too long learning curve...
And it's difficult to build test environment...
If you are a expert, this is no matter...
And there are not data it will be able to refer...
Vault is only reference site..
If someone share reference data(real verification project)...
We adopted specman for verification tool.
And it found some bugs which couldn't find on logic simulation and fpga board test.
However it's so difficult..
I hope Specman user will change good information in this forum...
artisan calculation
Nobody, Thanks a lot...
The latest verilog-xl don't also accept edge sense description.
After using perl script, i didn't got sdf annotation error.
Anyway, who has tsmc 0.18um design kit?
sdfa warning: negative timing check limit
There is no mismatch between netlist and sdf.
When I using ModelSim, there is no annotation error.
This is error message from Verilog-XL.
Who has design kit from Global UniChip, PGC and Sota?
If anyone has it, please give me...
sdfa error: could not find path
The followings are some error messages and relevant sdf.
L386888: SDFA Error: Could not find path S0 to Y in instance top.xtop.U57
L386889: SDFA Error: Could not find path S0 to Y in instance top.xtop.U57
(CELL
(CELLTYPE "MX2XL")
(INSTANCE U57)
(DELAY...
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