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port map others
Hi,
You can try to move the follow lines out of process;
dff3: DFF port map(clk,in_sig3,in_sig2);
dff2: DFF port map(clk,in_sig2,in_sig1);
dff1: DFF port map(clk,in_sig1,in_sig0);
dff0: DFF port map(clk,in_sig0,out_sig);
regards,
you can't use inportb() and outportb() in windows,but you can try to access vitural COMM by windows API.
check microsoft MSDN for more information.
or Search www.google.com by keyword:CreateFile CloseHandle ReadFile WriteFile
bobsanjose,
you should design a glue logic between CPU and nand flash to mimic nand as a Sram.
See the appnote 'Operating a NAND Flash Device Through an FPGA',
**broken link removed**
regards,
I need to synthesize verilog HDL 、VHDL and EDIF files into one FPGA.
Does someone known how to synthesize mixed HDL files in Quartus II?
Thank you in advanced,
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