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Recent content by Wheatley

  1. W

    Simulating Verilog Functional code in Virtuoso ADE

    Hi, Is it possible to simulate Verilog Functional code (not compiled) in Virtuoso ADE? Thanks in advanced!
  2. W

    [SOLVED] [moved] Delaying a square signal

    I solved this issue with a fully digital circuit made up of a binary counter and a simple FSM. If I have time I'll upload a document just in case anyone has a similar problem. Thanks!
  3. W

    [SOLVED] [moved] Delaying a square signal

    Well this circuit is intended for tuning a 1 G٠active resistor. Using an RC+comparator delay would be an endless loop ��
  4. W

    [SOLVED] [moved] Delaying a square signal

    Re: Delaying a square signal Sorry!! Thanks for your help.
  5. W

    [SOLVED] [moved] Delaying a square signal

    Re: Delaying a square signal That's my point. For a 50 us delay with 2 a pF capacitor, one would need a 36 MΩ resistor (quite big to be integrated with standard high-res poly).
  6. W

    Subthreshold biasing circuit

    What's the bias current value and what dispersion are you obtaining?
  7. W

    Simple differential amp design

    Could you post the simulation setup and all nodes DC voltages?
  8. W

    [SOLVED] [moved] Delaying a square signal

    Re: Delaying a square signal Hi Klaus, I think that the delay time is quite long for an RC-delay. It would probably requiere a MOhm resistor and I am looking for a fully integrated solution. Thanks!
  9. W

    [SOLVED] [moved] Delaying a square signal

    Hi, I want to delay a variable-frequency square signal for about 50-100 us (too much time for implementing it with inverters). How can I do this? Maybe some kind of D-latch with other stuff? Thanks! PD: I don't have access to digital design-synthesis-P&R tools, so the design have to be...
  10. W

    Using AMS pads on Virtuoso Layout L

    I do not understand how the AGND3ALLP pad could have other connections besides the pad opening.
  11. W

    Using AMS pads on Virtuoso Layout L

    The pad AGND3ALLP is connected to gnd! via the PIN PAD layer. This way, and with the connection of AVDD3ALLP, I assume that all the rest of the pads are correctly biased.
  12. W

    Using AMS pads on Virtuoso Layout L

    Hi, I am trying to include AMS pads (process AMS C35B3C3) in my layout but I am getting the BAD_SUBSTR_SUBTAP_FLOAT_ERC error when running Assura DRC. Regarding the pins, I am using the PIN PAD layer and I am naming the power and ground pins "vdd3r!" and "gnd3r!", respectively. Why am I...
  13. W

    [SOLVED] Extremely high leakage current in PMOS with AMS 0.35 um technology

    Thats it! I've changed min to 1e-18 and everything is working as expected. The nwell-psub junction behaves as a reverse-biased diode. I am measuring the current flowing into the nwell terminal and the current flowing from the psub terminal (they coincide). The other 3 terminals have no current.
  14. W

    [SOLVED] Extremely high leakage current in PMOS with AMS 0.35 um technology

    Wow, you think that Cadence is adding a transconductance of 2 pS between the n-well and the p-sub, right? I don't have access to the Cadence machine until tomorrow, so I'll reply in 12 hours! Thanks!
  15. W

    [SOLVED] Extremely high leakage current in PMOS with AMS 0.35 um technology

    Of course. I'll show three screenshots for illustrating the problem. First, this is the layout of a PMOS transistor with its 4 terminals and 1 terminal (labeled as gnd) corresponding to the p-sub tap. Second, this is the testbench I am running. Third, this is the current flowing from the...
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