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Recent content by whaleeee

  1. W

    Help tracking down very long synthesis time

    That is quite insightful, thanks! In retrospect, it does seem like my original code would be an improper use of a case statement. I suppose the priority nature of an if/elsif statement somehow takes care of this issue, but I need to think about it more.
  2. W

    Help tracking down very long synthesis time

    Ok, so I have solved the issue of the long synthesis time, though I'm not sure why. I sidelined the bit of code I posted originally and moved on to some other areas of my project I needed to work on. I rewrote a rather large if-elsif structure into a case statement for readability purposes...
  3. W

    Help tracking down very long synthesis time

    This is for synthesis only. Implementation actually doesn't take any longer whether this code is generated or not. I did think it might be something with using two different clocks, but as a test I had both processes use the same clock, but this did not make a difference.
  4. W

    Help tracking down very long synthesis time

    It is an array of 32-bit SLVs type test_ram is array (7 downto 0) of std_logic_vector(31 downto 0); signal test_ram_inst : test_ram;
  5. W

    Help tracking down very long synthesis time

    I am using Vivado 2015.4 to synthesize my code. I have a small section of code that I use for debugging and it causes synthesis to take > 30 minutes, whereas, if I don't include this part of the code, synthesis takes about 3.5 minutes. I know from experience that problems like this are hard to...

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