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Anyone? The chips are the only through hole CPLD devices stocked at both Mouser and Digi-Key. Judging by the quantities available someone has been buying them. Surely someone must know something about them???
I'd like to program an ATF750LVC CPLD device. According to the datasheet it is a "superset" of GAL22V10, however none of the affordable programmers list the ATF750 chips, so I don't know if they are programmed the same way.
I used the WinCupl software to describe my logic, simulate and build a...
As often is the case with digital systems, there can be more than one valid solution. At this point the main challenge in my project is having too many choices of ways to implement.
Fast synchronous SRAM solves the problem of reading and writing pixel data at the same time, but creates a timing...
The planned output datarate is up to 56MHz on output. (maybe 112MHz, but not mandatory)
Actual data width is 12 bits, closest common data width is 16 bit word, I guess.
For size I need 1M words.
So 1Mx16=16Mbit
I need to traverse the data in a loop twice, so I don't see how I could use FIFO...
I've got the following scenario:
First FSM on FPGA controls writing of continuous stream of digital pixel data, data goes into port 1 of some SRAM
Second FSM on FPGA controls reading of the data on port 2 of some SRAM, data read is double rate of input (with repetition)
Is there an SRAM that...
Re: Some advices in acurracy for a frequency counter using a spartan 6 fpga
Yes, that's probably the simplest way to do it.
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Using FPGA for this project is a bit much.
For example this functionality was built on a PIC18 controller of Bus Pirate...
Re: Some advices in acurracy for a frequency counter using a spartan 6 fpga
I don't think you understood what I was suggesting. I wasn't talking about the UART, UART is a really boring component you can either implement on FPGA using existing source or use external hardware, both solutions...
Re: Some advices in acurracy for a frequency counter using a spartan 6 fpga
Well, I figured you'd be sampling your signal continuously and your FPGA would be pushing out data at regular interval, that way you won't have to worry about two way communication, only one way. That's up to you...
Re: Some advices in acurracy for a frequency counter using a spartan 6 fpga
You can push your data out of serial port with a simple FSM very easily. 100ms is not a problem at all.
I don't know what your intended application is, but if you just wanted to capture and see the data a software...
Oh, I agree. It's only a few cents difference so strictly from cost standpoint probably not worth changing, but I would adapt it to one of the 14-pin PICs from the 16F family if I wanted to spend time on that.
I was wondering if it's possible to program a Lattice MachXO2 FPGA with something generic that I already have laying around. I intend to use FPGA's internal flash for configuration bitstream.
MachXO2 can be programmed using JTAG, master/slave SPI, I2C, Wishbone.
I have the following...
That's a possibility. I also found variations of this sort of thing for fewer digits and less pins. Still, makes a simple thing more complex.
What I'm looking for used to be made, and even in SMD. But I will avoid creating a design that would rely on NOS chips.
This almost calls for a PIC...
My bad, you mentioned the chip part in your code comment.
Well that's unexpected. Different vendors have different pin definition. For ISSI SSRAM /ADV is address advance, while for Micron PSRAM /ADV is address valid (latch).
Try adjusting /ADSP and /ADSC timing. Try delaying a few ns.
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