Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by wh_timme

  1. W

    [SOLVED] Design Compiler Error: Cannot open cell xxxxx.FRAM for read. (MW-004)

    The library under "astro" directory may be out of date for a DCT/DCG milkyway format. I recommend that you generate a new one using Synopsys Tech TF & Cadence LEF. Simply execute "Milkyway" in shell ---> "Create Library" --> "LEF IN"
  2. W

    [SOLVED] Design Compiler Error: Cannot open cell xxxxx.FRAM for read. (MW-004)

    It looks like the milkyway reference library (../../my_used_libraries/saed90nm_dv) is not a valid one. Is this library provided by the foundry or generated by yourself using Synopsys Tech TF & Cadence LEF?
  3. W

    Design Compiler(DC) Optimization commands to reduce negative slack?

    The DC optimization mechanism is based on cost. There're 3 costs that are timing related: WNS Cost, Max Delay Cost & Endpoint TNS Cost. The Max Delay Cost will not be printed unless you set the "compile_log_format" variable. You can modify Max Delay Cost by using "group_path" command, and...
  4. W

    PreCTS timing drv fixing

    Only the WNS Optimizer has the "give up" mechanism: When the WNS Optimizer cannot find further improvements for WNS, it quits & triggers refinePlace. If TNS gets worse after refinePlace, the WNS Optimizer will be restarted again for another iteration, that is, the tool does not "give up". Both...
  5. W

    PreCTS timing drv fixing

    "optDesign" command will call the following five optimizers in multiple iterations: Global Optimizer Area Reclaim DRV Optimizer TNS Optimizer WNS Optimizer while "optDesign -incr" command only calls the WNS Optimizer (and maybe Area Reclaim). For EDI 14.2 and Innovus, clockDesign will call...
  6. W

    How to stop design compiler logic optimization ?

    Here're some techniques if you don't want to modify your HDL hierarchy: 1. If your HDL Structure is preserved after Elaborate, you can set_dont_touch on relevent nets(Remember to set "enable_keep_signal_dt_net" to true or the design won't be mapped!) or alternatively use "set_dont_touch_network...

Part and Inventory Search

Back
Top