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Recent content by Websterskimo

  1. W

    A question to DC(set_input_delay and set_clock_latency)

    set_input_delay hi set_input_delay means delay that ideal source to input port delay and set_clock_latency means that we estimate postlayout clock tree latency. My question is comming.What is the fllowing three command different(I think that first command is the same as third command, true?)...
  2. W

    Why loop bandwidth must be below reference in Adaptive-PLL?

    One Adaptive-PLL problem Recently i study some PLL papers. I encounter some questions and try to find some books to know, but has no uses. The problem is that why "loop bandwidth must be at least a decade below the reference frequency in order to avoid instability due to the sampling delay"...
  3. W

    Who can help me ? thank for you help!!!

    HI I try to download the code, but i can't do it. thanks

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