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I am planning to develop WiFi RF-SoC Chip, and our focus & speciality are Radio and RF Transceiver design. We are looking for potential co-operation or partner whose speciality are WiFi PHY/MAC, especially who or which company can provide Silicon-proven WiFi PHY/MAC IP or prototype.
Bluetooth is...
Hi Liuguojia387, Which Process you used, 65nm or 130nm? 12b 1GSps DAC with SFDR of 70dB? Though It is so popular a design, Switches and current cell may be the same as those used in 100MHz ~ 200MHz Cases. My understanding, the most tricky things to handle is high frequency Dynamics and Power...
3 Weeks, for just Circuit design? It's not a easy job I think, of couse It depends on what kink of Filter Spec you need, Such as SFDR.
BTW, in 90nm CMOS, 120MHz Fc Filter can also be implemented by Active-RC Topology, If a tough Linearity Specification is needed.
simulation of switched caps noise
You can search 'Ken Kundent' by Google or go to www.designers-guide.org. I remember he had write a good paper on this topic.
mdac pipleline
Hello iamxo,
Yes, you cannot run a Full-scale transient to verify MDAC SNDR, My suggestion is that you can do it in ADC top-level simulation, Just MDAC use circuit, all the others use verilog-a model.
Indeed, you just need to check your settling behavior, FFT results comes from it.
Re: dc offset problem
Hi,
I wonder why your loop circuit sensitive to load, it seems Sever loop DC-offset cancelling circuit will be okay in your case.
You can use "cmdmprobe" for your closed-loop stability simulation, you can find it in Cadence "basic" Library.
Where there is a loop , there is stability issue. So, principlely you should check every loop in your design. In fact , stability will not a big issue in Active-RC filter design.
if You are going to find a job in analog design, ADC is always a must.
while in RF design, PLL absolutely much critical.
sigma-delta PLL and Digital PLL maybe a good topic.
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