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Recent content by wannaknow

  1. W

    Can I do data buffering and data plotting at the same time?

    Thank you for your reply. The Matlab serial port receive rate is 11Hz. please refer to the image below, the Nios II sends data to uart, Matlab access the serial port and plot the below sinusoidal waveform. My problem is, a complete cycle of sinewave obtained from fpga is with a frequency of...
  2. W

    Can I do data buffering and data plotting at the same time?

    thanks for your reply... "b. the best thing for you is to do the buffering with your vhdl code, cpu will just read the data.", thank you for the suggestion, I would like to go for this, as I am more familiar in programming nios system in C code, do you mind to tell abit on how to do the...
  3. W

    Can I do data buffering and data plotting at the same time?

    I am using Quartus 12.1 sp1, vhdl and Altera Nios II programmed in C code for DE0-Nano Development. Basically, what I have is, data is sent from fpga vhdl block to NIos II system, Nios II system sends the data to serial port, Matlab access the serial port to real time plot the graph. I am...
  4. W

    Why do I need on-chip fifo memory core for buffering?

    I dont know if this is feasible. What I am tempted to do, since the rate I can plot a graph is slower than the rate the incoming signal is read. If I know the beginning of every incoming signal let say this point is indicated by a count=0, everytime I detect count=0, I know it is the beginning...
  5. W

    Why do I need on-chip fifo memory core for buffering?

    Thank you for your reply. Regarding your last paragraph, the rate the data is sent to serial port (50Hz) is way faster than the serial port can receive (8Hz), my question is, how by using say buffering in SDRAM will help in this context? By doing so, I will still be losing some of the cycles...
  6. W

    Why do I need on-chip fifo memory core for buffering?

    Hi, I have an issue where the rate the data is sent to serial port (50Hz) is way faster than the serial port can receive (8Hz). Basically, what I have is, data is sent from fpga vhdl block to NIos II system, Nios II system sends the data to serial port, Matlab access the serial port to real...
  7. W

    How to select parameters for Equivalent Time Sampling

    The reason I am asking this question is that, I think I am doing the ETS in some sense, resulting in correct output being plotted in Matlab. But I have no idea whether ETS is implemented in Nios ii or in Matlab? I am sending data from fpga (nios ii processor) to serial port and Matlab access...
  8. W

    How to select parameters for Equivalent Time Sampling

    Hi, I have a Nios system with Qsys components such as Interval timer, UART, SDRAM and some PIOs. My system specifications are DE0 Nano, Quartus 12.1 sp1, Altera monitor program. Nios II system are interfacing with several VHDL blocks. I am able to read data from FPGA to Nios processor, then...
  9. W

    How to read signed values from FPGA in VHDL to Nios II system

    thanks, if I understand correctly, you mean this line (data <= to_slv(resize(scale*to_sfixed(in, 0, -11), 7, -6));) here, I still resize it to 14 bit because I did extend the sign extension in C code, meaning the input to the C code is still 14 bits. I also tried with another approach where I...
  10. W

    How to read signed values from FPGA in VHDL to Nios II system

    Like you said, I use 16 bit signed with a scale factor of 1/64 to get the 6 fractional points...I managed to get this value converted correctly to floating point, but still I am having issue in #7, I thought they are not relevant that is why I created a new thread
  11. W

    How to read signed values from FPGA in VHDL to Nios II system

    Hi, thank you for your reply, I just read this reply... I did give this a try, I still am getting the same output as in #7 where the output voltage and current keep changing , since I could not edit my original post, I have updated the content in #7. Does it have anything to do with timing or...
  12. W

    How to read signed values from FPGA in VHDL to Nios II system

    Data transfer between fpga block (14 bits) in vhdl and Nios II system (16 bits) Hi, I am writing C code to program Altera Nios II system in Cyclone IV E. The Nios II system is used to control some custom FPGA blocks written in VHDL in Quartus II. In the vhdl block "a", "data" is defined as...
  13. W

    How to read signed values from FPGA in VHDL to Nios II system

    Thanks for your reply... But, the 14-bit data can be positive, zero or negative. The 14-bit-data is defined as follow: with msb as the sign bit, the following 6 bits are the magnitude for integer and the last 6 bits are the magnitude for fractional part. I need to compute the real value of...
  14. W

    Convert binary (integer and a fraction) from vhdl to decimal in C code, negative value

    Re: How to read a 16-bit data into string in C code Thanks for your reply, forgive me for didnt make it clear enough. I need to compute the real value of this binary representation into a decimal value of BOTH integer and fraction, for example, the value is 15282 (0011 1011 1011 0010), but...
  15. W

    Convert binary (integer and a fraction) from vhdl to decimal in C code, negative value

    How to read a 16-bit data into string in C code I have a 16-bit data that is fed from FPGA in vhdl, the NIos II processor reads the 16-bit data from FPGA and do some processing tasks, where Nios II system is programmed in C code How could I read this 16-bit data in string? printf("%d"...
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