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Recent content by wangyuestc

  1. W

    Help needed about subthreshold circuit design!

    Hi nitishn, In fact, the measured output voltage of the regulator is higher than the simulated value. For the oscillator, there is no high impedance node connected to a pin.
  2. W

    Help needed about subthreshold circuit design!

    Hi Jkatic, I will try the MC. But there is no resistors in the regulator, the resistors in the schematic is diode connected pmos working in subthreshold. And we have measured about 20 chips, the Vout of the regulator(which is supposed to be 1.8V) is around 1.9~2V for all chips. That is weird.
  3. W

    power supply vs. technology

    For TSMC 0.18um CMOS technology, the Vgs Vds of 1.8V MOS devices should < 1.8V, the Vgs Vds of 3.3V MOS devices should < 3.3V.
  4. W

    Help needed about subthreshold circuit design!

    I use the oscillator topology presented in this paper.
  5. W

    Help needed about subthreshold circuit design!

    I have simulated TT FF SS for the regulator and osc with the model in the pdk. I have also simulated TT FF SS FS SF for the osc with a changed model according to the PCM DATA.
  6. W

    Help needed about subthreshold circuit design!

    Hi, I am working on the design of some subthreshold circuits based on TSMC 0.18 cmos process. But there is huge difference between the simulation and measured results. I designed a regulator(power consumption=1uW) based on the subthreshold voltage reference proposed in the paper "A 300 nW, 15...

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